1. Field
Example embodiments relate to transistor layout structures for controlling the sizes of transistors and methods of controlling the same. Also, example embodiments relate to transistor layout structures for controlling the sizes of transistors, without changing an active region, in a metal wiring process and methods of controlling the sizes of the transistors.
2. Description of Related Art
In general, the size of a transistor is typically decided by the width W and length L of a channel that are the width and length of a zone forming the channel. The size of a transistor is related to the size of an active region. When the active region is big, the size of the transistor is big, and when the active region is small, the size of the transistor is small. That is, generally, the size of an active region is controlled to control the size of a transistor.
FIG. 1 is an equivalent circuit diagram of a conventional PMOS transistor, and FIG. 2 is a layout diagram of the transistor of FIG. 1.
As illustrated in FIG. 1, a general PMOS transistor P comprises a source/drain region B, a gate A, and a drain/source region C. The PMOS transistor has predetermined width W and length L of a channel.
Reference marks “B” and “C” do not directly indicate the drain and source region. These marks denote metal wires connected to the drain and source regions. Since FIG. 1 is an equivalent circuit diagram, the metal wires are identically illustrated.
The transistor of the equivalent circuit as illustrated in FIG. 1 has a conventional layout structure as illustrated in FIG. 2. As illustrated in FIG. 2, an active region ACT in a predetermined size is arranged on a semiconductor substrate. A gate line A across the active region ACT is arranged on the active region ACT. The active region ACT is divided into two by the gate line A, and the two divided regions are a source region and a drain region.
The width of the gate line A is a channel length L of the transistor, and the width of the active region ACT in a direction of the length of the gate line A is a channel width W of the transistor. Generally, the size of the transistor has been controlled by controlling the width of the gate line A and the width of the active region ACT. That is, transistor manufacturers have decided the size of the active region by design and have manufactured transistors in a desired size by realizing the size of the active region through the layout structure like FIG. 2.
However, when the size of a transistor is different by wrong design or defects during a transistor manufacturing process, a wafer which is subject to a manufacturing process is to be destroyed, and a new wafer needs to be again manufactured after the design is again made or the defects upon manufacture are corrected. Specifically, in FIG. 2, when the size of a transistor needs to be controlled after upper wires connected to each of the source/drain regions through a contact CT, i.e., the metal wires B and C, are formed, all of these should be abandoned and a layout is to be again designed, to manufacture a transistor. Therefore, the manufacturing cost increases and the efficiency of production decreases.
In this regard, a technique is needed to control the size and the like in a transistor in the manufacturing process. This is called a revision process. It is most favorable that the revision process is performed in the final step of the transistor manufacturing process. When the revision process is performed in the beginning step of the transistor manufacturing process, the transistors being in the processing steps in which the revision process cannot be performed in the processing steps following the beginning step should be abandoned. However, when the revision process is performed in the last step of the transistor manufacturing process, the transistors in all of the processing steps are usable.
Therefore, a layout designing technique is required to make it possible to perform the revision during the latter half of a manufacturing process.